1. Field of the Invention
This invention relates to packaged semiconductor devices and methods for manufacture thereof. More particularly, the invention pertains to ultrathin devices having a small footprint and simplified processes for their manufacture including device packaging at the wafer scale.
2. Description of the Related Art
Solid state electronic devices, more colloquially known as semiconductor chips or dice, are typically manufactured from a semiconductor material such as silicon, germanium or gallium/arsenide. Circuitry is formed on one surface of the device with input and output (I/O) pads formed around the periphery or centrally positioned to facilitate electrical connection with a host electrical apparatus.
A profusion of small electronic consumer products includes pagers, notebook computers, cellular telephones, digital cameras, modems, global position systems and electronic watches, to name a few. The rapidly growing consumer demand for small product size and low profile products drives the search for ways to construct smaller, thinner, more powerful semiconductor devices. The development of inexpensive, ultra-thin, compact devices is needed to enable the proliferation of large numbers of miniature electronic apparatus in the near future.
Currently, semiconductor chips are typically packaged to protect the chip from mechanical damage, external contamination and moisture. Most commonly, semiconductor chips are encapsulated, i.e. packaged within a polymeric material which sometimes provides opportunity for moisture ingress, gas diffusion, corrosion, etc. Thus, plastic encapsulated chips may be subject to performance degradation and abbreviated life.
Ceramic encapsulation provides a higher level of protection for the chip. However, the process is more complex and results in an expensive package of increased size.
Sealing of the semiconductor chip active circuitry at the wafer stage is known. In this process, a passivation coating of ceramic materials such as silica and/or silicon nitride may be applied by chemical vapor deposition (CVD). However, the subsequent etching back of the passivation coating at the bond pads of the semiconductor chip may damage the coating around the bond pads, resulting in a non-hermetic seal and permitting corrosion to deleteriously affect chip reliability and life.
U.S. Pat. No. 5,336,928 of Neugebauer et al. discloses a hermetically sealed device construction.
U.S. Pat. No. 5,455,459 and 5,497,033 of Fillion et al. disclose systems for enclosing and intercolimecting multiple semiconductor chips.
U.S. Pat. No. 5,481,135 of Chandra et al. discloses the use of ceramic materials in hermetically sealed device packages.
U.S. Pat. No. 4,769,345 of Butt et al., U.S. Pat. No. 4,866,571, 4,967,260 and 5,014,159 of Butt, U.S. Pat. No. 5,323,051 of Adams et al., and
U.S. Pat. No. 4,821,151 of Pryor et al. disclose the use of glass in the packaging of certain types of semiconductor devices.
U.S. Pat. Nos. 4,749,631 and 4,756,977 of Haluska et al. disclose ceramic and ceramic-like compositions which may be used for coating electronic devices.
In U.S. Pat. No. 5,682,065 of Farnworth et al., a fully hermetically sealed semiconductor chip is disclosed. The bare die is covered with a coating of glass using a spin-on-glass (SOG) process, a dip process or flow coating. The glass is applied as a mixture of small glass particles and a polymeric carrier, and subsequently heated to evaporate solvent(s) from the mixture and harden the applied material. Also disclosed are steps of thinning the wafer.
U.S. Pat. No. 5,547,906 of Badehi discloses a method for forming semiconductor chip packages with edge connections. The step of singulation with a cutting tool exposes the array of contacts. A glass may be used as covers sandwiching the chip therebetween.